1. Field of the Invention
The present invention relates to the implementation of a programmable divider. It more particularly applies to the implementation of a frequency divider which divides a pulse train of a given frequency by an integer number, thereby generating a pulse train, of which the duty ratio or duty cycle is between a third and half a period of the original pulse train. An example of application of the present invention relates to the generation of pulse trains for monitoring infrared-emitting diodes of a remote control.
2. Discussion of the Related Art
A programmable frequency divider is generally implemented based on a programmable asynchronous counter including flip-flops, for example, D flip-flops. The flip-flops generally are mounted in cascade, one output of a flip-flop being connected to one clock input of a next flip-flop. The number of flip-flops correspond to the number of bits over which the counting is performed. A first flip-flop receives, on its clock input, a clock signal, the frequency of which is desired to be divided.
The structure and operation of this type of programmable counter is well known in the prior art and only the features necessary for the understanding of the present invention will be indicated hereafter.
A counter of a programmable divider generally operates as a down-counter, that is, its programming consists of loading each of the flip-flops with a high or low state, the combined respective loading states of the flip-flops representing the binary division ratio. The counter is generally associated with a circuit for detecting the transition through zero of the counter's counting value. This detection is used, in particular, for inducing a cyclic reloading of the binary division ratio.
FIG. 1 shows a first example of a conventional programmable counter.
Such a counter is, for example, a counter CNT 1 having five bits issuing five counting signals DEC0 (rank0), DEC1 (rank1), DEC2 (rank2), DEC3 (rank3), and DEC4 (rank4) corresponding to the respective outputs of the flip-flops (not shown) constitutive of counter 1. A clock input receives a clock signal CLK0, the frequency of which is desired to be divided by an integer i. Number i is programmed by means of five binary signals I0, I1, I2, I3, and I4 sent to the respective inputs of the flip-flops of counter 1. Signal I0 corresponds to the least significant bit. The loading of ratio i is obtained by an edge, for example a rising edge, of a signal LOAD which causes a simultaneous loading of the states of signals I0 to I4. Signal LOAD generally is obtained by a circuit (not shown) for detecting a simultaneous low state on all signals DEC0 to DEC4.
The desired clock signal, the frequency of which corresponds to the frequency of signal CLK0 divided by ratio i, is directly taken from one of the outputs of the counter by selecting one of signals DEC0 to DEC4 which has a rank corresponding to the most significant bit of ratio i.
FIG. 2 illustrates the operation of a counter such as shown in FIG. 1. This drawing shows, in the form of timing diagrams, the shape of signals CLK0, DEC0, DEC1, DEC2, and LOAD when counter 1 is programmed to count to seven.
The respective states of signals I4 to I0 are, in this example, 00111. For each rising edge of signal LOAD, signals DEC0, DEC1, and DEC2 switch to the high state independently of their previous state. Signals DEC3 and DEC4 have not been shown in FIG. 2, they permanently remain in the low state, the most significant bit of ratio (i=7) being carried by signal DEC2.
For each rising edge of signal CLK0, the binary number issued by signals DEC2 to DEC0 is decreased by 1 until a new rising edge of signal LOAD reloads the flip-flops with number 00111.
Signal DEC2 issues a signal having a frequency which is divided by seven with respect to that of signal CLK0.
The direct use of one of the counting signals of such a counter is a particularly simple way of obtaining a frequency division. However, the duty cycle (duration of a pulse for a period) of the clock signal obtained varies considerably according to the division ratio. For example, for a divider over five bits, it is between 6.25% (cyclic ratio of one sixteenth) for a division by sixteen and 66% (cyclic ratio of two thirds) for a division by three.
In some applications, it is necessary that the duty cycle of the signal obtained be maintained in a range of values between 33% and 50%. This is for example the case for infrared remote controls where pulse trains are used to monitor infrared-emitting diodes, and where the duty cycle of the pulses has to be between two standardized values of 33% and 50%.
FIG. 3 shows an example of a conventional programmable divider producing a duty cycle between 33% and 50%, when the division ratio is between two and thirty-two.
Such a divider includes two programmable counters, respectively 2 and 3, which are identical over four bits and are triggered by the same clock signal CLK0, the frequency of which is desired to be divided. Counters 2 and 3 are programmed (by signals I0 to I4 and I'0 to I'4) so that the sum of their respective counting thresholds corresponds to the desired division ratio i. A circuit (not shown) for detecting the counting threshold, by detection of a transition through zero of the counting value, is integrated in each of counters 2 and 3. Here, signals S2 and S3 issued by the respective detection circuits 2 and 3 generate the desired clock signal. Signals S2 and S3 are respectively sent on set and reset inputs of a bistable latch 4, an output S of which issues the desired clock signal. Signal S2 further is sent to load control input LOAD of counter 3 and signal S3 further is sent to load control input LOAD of counter 2.
FIG. 4 illustrates the operation of such a programmable divider. This drawing shows, in the form of timing diagrams, the shapes of signals CLK0, S2, S3 and S for a division ratio of seven. The states of signals I0 to I4 and I'0 to I'4 are, respectively, 0100 and 0011.
At a time t0 where signal S2 switches to the high state, signal S switches to the high state and value 0011 is loaded into counter 3 which then starts to count down to set the duration of the pulse of signal S. At a time t1 when signal S3 switches to the high state, signal S switches to the low sate and value 0100 is loaded into counter 2 which then starts to count down to set the interval between two successive pulses. When signal S2 switches again to the high state (time t2), a new pulse of signal S starts. The switching to the low state of signal S2 or S3 occurs, unless appropriate signals (not shown) for initializing counters 2 and 3 are used, at the latest at the loading of the counting threshold into the counter involved, as is shown in FIG. 4.
Such a divider can generate a duty cycle between 33% (for a division ratio of three) and 50% (for a division ratio of two), but it has the disadvantage of requiring two programmable counters.